Product Summary

The W986432DH-6 is a high-speed synchronous dynamic random access memory (SDRAM), organized as 512K words × 4 banks × 32 bits. Using pipelined architecture and 0.175 mm process technology, the W986432DH-6 delivers a data bandwidth of up to 800M bytes per second (5). For different application, the W986432-DH7 is sorted into four speed grades: -5, -55, -6, -7,-8. Accesses to the SDRAM is burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.

Parametrics

W986432DH-6 absolute maximum ratings: (1)Input, Column Output Voltage, VIN, VOUT: -0.3 to VCC +0.3 V; (2)Power Supply Voltage, VCC, VCCQ: -0.3 to 4.6 V; (3)Operating Temperature, TOPR: 0 to 70℃; (4)Storage Temperature, TSTG: -55 to 150℃; (5)Soldering Temperature (10s), TSOLDER: 260℃; (6)Power Dissipation, PD: 1 W; (7)Short Circuit Output Current, IOUT: 50 mA.

Features

W986432DH-6 features: (1)3.3V ±0.3V power supply; (2)524288 words × 4 banks × 32 bits organization; (3)Auto Refresh and Self Refresh; (4)CAS latency: 2 and 3; (5)Burst Length: 1, 2, 4, 8, and full page; (6)Sequential and Interleave burst; (7)Burst read, single write operation; (8)Byte data controlled by DQM; (9)Power-down Mode; (10)Auto-precharge and controlled precharge; (11)4K refresh cycles/64 mS; (12)Interface: LVTTL; (13)Packaged in 86-pin TSOP II, 400 mil - 0.50.

Diagrams

W986432DH-6 circuit diagram

W986408AH
W986408AH

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W986408BH
W986408BH

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W986408CH
W986408CH

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W986416AH
W986416AH

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Negotiable 
W986416BH
W986416BH

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Negotiable 
W986416CH
W986416CH

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Data Sheet

Negotiable