HYB25L256160AF-7.5

Product Summary

The HYB25L256160AF-7.5 is a low power, four bank synchronous DRAM. It is organized as 4 banks x 4 Mbit x 16 with additional features for mobile applications. The HYB25L256160AF-7.5 achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The HYB25L256160AF-7.5 adds new features to the industry standards set for synchronous DRAM products. Parts of the memory array can be selected for Self-Refresh and the refresh period during Self-Refresh is programmable in 4 steps which drastically reduces the self refresh current, depending on the case temperature of the components in the system application.

Parametrics

HYB25L256160AF-7.5 absolute maximum ratings: (1)Voltage on I/O pins relative to VSS VIN, VOUT: –1.0 to VDD + 0.5 V; (2)Voltage on I/O pins relative to VSS VIN, VOUT: –1.0 to +4.6 V; (3)Voltage on VDD supply relative to VSS VDD: –1.0 to +4.6 V; (4)Voltage on VDDQ supply relative to VSS VDDQ: –1.0 to +4.6 V; (5)Operating Case Temperature (extended) TCASE: –25 to +85 ℃; (6)Storage Temperature (Plastic) TSTG: –55 to +150 ℃; (7)Power Dissipation PD: 0.7 W; (8)Short Circuit Output Current IOUT: 50 mA.

Features

HYB25L256160AF-7.5 features: (1)16 Mbits × 16 organisation; (2)Fully synchronous to positive clock edge; (3)Four internal banks for concurrent operation; (4)Data mask (DM) for byte control with write and read data; (5)Programmable CAS latency: 2 or 3; (6)Programmable burst length: 1, 2, 4, 8, or full page; (7)Programmable wrap sequence: sequential or interleaved; (8)Random column address every clock cycle (1-N rule); (9)Deep power down mode; (10)Extended mode register for Mobile-RAM features; (11)Temperature compensated self refresh with on-die temperature sensor; (12)Partial array self refresh; (13)Power down and clock suspend mode; (14)Automatic and controlled precharge command; (15)Auto refresh mode (CBR); (16)8192 refresh cycles / 64 ms; (17)Self-refresh with programmble refresh period; (18)Programmable power reduction feature by partial array activation during self-refresh.

Diagrams